There is growing interest in developing new hardware architectures to complement or replace existing static architectures, and recently there has been a theoretical direction to explore the richness of nonlinear dynamical systems to implement reconfigurable hardware (dynamic).
The present invention is to use a nonlinear dynamic system to emulate different logic gates, which are the basis for general-purpose computing, and after obtaining the logic gates, integrate these elements into a programmable device by the user, ie for create a dynamic array of logic gates. In the prior art there are some related technology developments such as the following:
U.S. Pat. No. 5,646,546A (U.S. Pat. No. 5,748,009A) consisting of a programmable logic cell generated by four logic gates, where two of which are configurable. The two configurable logic gates are located near the entrances of the logic cell. Each configurable logic gate has two inputs, each input is connected to one of the four inputs of the logic cell. The two remaining logic gates receive the outputs of the configurable logic gates. There are four independent input nodes, each of which has an associated programmable input multiplexer. Each input multiplexer could have inputs connected to at least two types of interconnecting conductors. The cell also has two output lines, each has an associated output multiplexer that controls the cell independently. The output of each output multiplexer is connected to an input of output multiplexer. Additional features include a multiplexer having inputs connected to two input nodes of the cell, an input selector connected to a third input node of the logic cell, and an output connected to an output node of the cell; a data system with low input distortion (eg clock) that has at least one input multiplexers; a flip-flop connected in the logic cell; and the internal feedback of the cell. The preferred programming method uses SRAM memory cells programmed by the user.
In the patent described above, the logic gates that are interconnected are programmable only through interconnection, so fail to set a dynamic array, where each perform multiple functions type AND, OR, XOR, NAND, NOR and NOT interchangeably, so they are fixed operations or configured by the initial pulse input to the cell.
A second patent relating to this technology is the U.S. RE35977E, consisting of a set of lookup tables for use in programmable logic devices modified to facilitate the use of such tables to provide adders (subtractors including) and various types of counters. Each lookup table is actually divided into smaller query tables when an adder or counter is required. A portion of the partitioned table is used to provide a sum output signal, while the other part of the partitioned table is used to provide a signal that can be applied immediately in the next stage of the adder or counter. If desired, each logic module includes a lookup table may further include logic circuitry for logically combining its normal output applied to its carry in input signal to provide a range of functions that have more inputs and may be accepted by a single logic module.
Unlike the technology proposed, arrangements do not require partitions to differentiate sectors of the tables, as in this patent differentiate the type of function that feed instructions; but it is based on a nonlinear system with any features that feeds.
A similar proposed arrangement is contained in U.S. Pat. No. 6,025,735A patent, such an arrangement is based on a matrix of programmable switching comprised of a series of elements arranged in rows and columns, in which a first, a second, and a third programmable switching element in the array of programmable switching elements include: a ferroelectric transistor having a control electrode, a first conduction terminal and a second conducting terminal, wherein the ferroelectric transistor provides a conduction path for transferring a signal through programmable switching element; a transistor programming having coupled a control electrode to receive a selection signal, a first current conduction electrode, and a second current conduction electrode coupled to receive a programming voltage to program the ferroelectric transistor either in a on or off state, the first programming transistor's driving current electrode is coupled to the control electrode of the ferroelectric transistor; and a first line programming, which provides the programming voltage coupled to the second programming transistor's driving current electrode in the first and third programmable switching element in the array of programmable switching elements; and a first selection line which supplies the selection signal coupled to the control electrode of the transistor programming in the first and second programmable switching elements in the matrix. This patent is practically focused on the wiring between logic gates.
Now, with respect to similar methods or processes, US20050073337A1 (U.S. Pat. No. 7,096,437B2, U.S. Pat. No. 7,415,683B2, U.S. Pat. No. 8,091,062B2), this patent comprises a dynamically configurable logic gate may include a controller configured to provide a reference threshold signal resulting in the first signal; an adder configured to sum the first reference threshold signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the summed signal processed in the chaotic updater. The logic gate can function as one of a plurality of different logic gates responsive to adjusting at least one of the reference threshold signals.
However, this instruction set obtains its technical feature in the corresponding programmed difference, which depends directly on the type of chaotic nonlinear system used.
US20110062986A1 patent, U.S. Pat. No. 7,973,566B2, US20100219858A1, U.S. Pat. No. 7,863,937B2 includes a set of elements that complements and becomes more complex the above patent, since an input of the logic gate receives at least one signal input logic gate and at least one control signal. At least one outlet to produce each output signal of the logic gate. A nonlinear updater works as a dynamically configurable element to produce a plurality of different logic gates selected by the control signal. Nonlinear updater includes a nonlinear output updater. Nonlinear updater is configured to apply a nonlinear function to the input signal of the logic gate to produce the output signal of the nonlinear updater that represents a logical expression being implemented by one of the plurality of different logic gates in input signal of the logic gate; A comparator includes a comparator input which is adapted to receive a threshold value of reference for producing the output signal of the logic gate based on comparing the nonlinear output signal with the reference threshold value.
The patent US20100219862 is a logic gate which is adapted to implement logical expressions. The logic gate includes at least one inlet which is adapted to receive an input signal and at least one control signal. At least one input signal and the control signal is a noise signal. At least one outlet is adapted to produce an output signal. Nonlinear updater works as a dynamically configurable element and produces multiple different logic gates selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. Nonlinear updater is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of several different logic gates in the input signal. This patent is related to chaotic computing, operation includes noise signals. Although the mechanism is described similarly technical feature is to be completely different, since the programmable nonlinear chaotic system that selects the output depends directly on this.
Patents US2008150578A1, US2011006807A1, U.S. Pat. No. 7,925,814 comprise a configurable logic gate that uses a nonlinear element. The dynamically configurable logic gate includes an input adder to receive a pair of input signals and generating the sum of said input signals input. In addition, the dynamically configurable logic gate includes a nonlinear element applying a nonlinear function to the sum of the input signals to produce a nonlinear output signal. The output signal of the dynamically reconfigurable logic gate corresponds to one of the different logic gates responsive to adjusting the sum of the input signals and/or the nonlinear function. The patent includes the dynamically configurable logic gate having feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and functions as one of different types of logic gates to produce an output signal corresponding to a memory element according to a selection control signal. It also discloses a matrix structure of dynamically configurable logic elements. This patent makes use of a nonlinear and chaotic system.
Patent US2008094103A1 in general protects the functionality of a multiplexer having m input ports only and performs the function of a multiplexer which has twice the predetermined input signals A1, A2, . . . , Aj, where j=2*m. The multiplexer functionality can be implemented using programmable device having one or more macrocells, an inverter and switches as antifuses. This patent relates to programmable logic modules and more specifically with the functionality of the multiplexers.
The patent US2008273831 consists of an optical logic gate which comprises two optical inputs for receiving two optical signals and an optical output that produces an optical signal, this signal represents the result of applying a logic function required. The logic gate is characterized by optical combinatorial means for mixing the optical signals and thus produce a corresponding combinatorial signal whose strength is the combination of the powers of the optical signals and non-linear optical means receiving the combined signal and output the optical signal departure. The logic function depends on the characteristic of nonlinear optical media. This patent relates to optical logic gates which are reconfigurable in terms of the logic function.
US2013002293 shows a dynamically reconfigurable logic gate with linear base, which is a device that allows logical outputs dependent configurable parameters set within the device. The device consists of three blocks: the first block receives at least one input signal and determines whether the signals are “high” or “low” compared with a reference threshold signal. The second block adds the logical signals of the first block with an offset signal. The third block determines if the sum at the second block is a low or high level by checking if the sum falls within a predetermined range. This patent is related to the dynamic computation and particularly to dynamically configurable logic gates structures with linear kernel.
The novelty of the proposed invention consists of a programmable array within the field of reconfigurable logic gates (FPRGA type) consisting of a device to implement complex logic functions. The design of a FPRGA is based on four main blocks: the reconfigurable logic gates, programmable rewiring, input interfaces and output interfaces. Each reconfigurable logic gate is a nonlinear system and can be configured to perform any of the following logic functions: AND, OR, XOR, NAND, NOR and NOT; programmable rewiring allows communication between other blocks of reconfigurable logic gates, and with the input and output interfaces; while input and output interfaces respectively serve to communicate signals from outside the device and vice versa. Current research exploits the characteristics of nonlinear dynamic systems through their electronic implementations, for example, those described in the patents or their respective publications identified as U.S. Pat. No. 8,091,062, U.S. Pat. No. 7,973,566, U.S. Pat. No. 7,924,059, U.S. Pat. No. 7,863,937, U.S. Pat. No. 7,415,683, U.S. Pat. No. 7,096,437, U.S. Pat. No. 7,453,285, U.S. Pat. No. 7,925,814 and the invention contained in the patent application US 2010/0219858 that are related to chaotic computing architectures for logic gates based on nonlinear systems; however, in the present invention are disclosed settable structures dynamically reconfigurable logic gates based on a nonlinear system without sensitivity to initial conditions, programmable interconnects, as well as blocks of input and output blocks. On the other hand, there are inventions and patents comprising modules which can be rewired to produce different outputs calculation, but these devices employ static logic gates.
Examples of this type of technology, field programmable gate arrays (FPGAs) where it is possible to reconfigure the arrangement by rewiring. This produces a limited flexibility in reconfiguring degree rewiring only and not reconfiguration of logic gates. Patents described in U.S. Pat. No. 6,025,735A, U.S. Pat. No. 5,646,546 and RE35977E, based on arrangements where static logic gates rewiring may have significant difference of configurable structures reconfigurable logic gates based on a nonlinear system presented in this application. FPGAs rewiring is based on different embodiments, for example the U.S. Pat. No. 7,482,834B2 has a programmable multiplexer, which allows rewiring.
Although the basis of these structures is a nonlinear system in this proposed structures have sensitive dependence on initial conditions, as does the chaotic circuit for a robust dynamic reconfigurable logic gate; therefore, a method, a circuit, a matrix, and the system to provide an implementation of a reconfigurable logic element using nonlinear system and an effective programmable rewiring between them were designed.